1. Field of the Invention
The present invention relates to a phase-locked-loop (PLL) and, more particularly, to a detector for detecting when an oscillating signal output by the PLL is locked to a reference signal input to the PLL.
2. Description of the Related Art
A phase-locked-loop (PLL) is a circuit that generates a periodic signal that is equivalent to a reference signal (the signals have the same frequency (equal pulse widths) and are in phase). The periodic signal can be directly output from an oscillator, or can alternately be formed by frequency-dividing the signal output from the oscillator.
FIG. 1 shows a block diagram that illustrates a conventional PLL 100 that utilizes a frequency-divided output signal. As shown in FIG. 1, PLL 100 includes a phase frequency detector (PFD) 110 that detects the difference in phase and frequency between a periodic feedback signal FBK and a reference signal REF. In addition, PFD 110 outputs an up signal UP and a down signal DN that are responsive to the difference in phase and frequency.
As further shown in FIG. 1, PLL 100 also includes a first current source 112 that sources a charging current IC, and a first switch 114 that is connected between first current source 112 and an input node IN. First switch 114, which is controlled by the up signal UP, defines the amount of the charging current that is allowed to flow into the input node IN. First switch 114 is commonly implemented with a MOS transistor.
In addition, PLL 100 also includes a second current source 116 that sinks a discharging current ID that is equal to the charging current IC, and a second switch 118 connected between the input node IN and second current source 116. Second switch 118, which is controlled by the down signal DN, defines the amount of the charging current that is allowed to flow out of the input node IN. Second switch 118 is also commonly implemented with a MOS transistor.
PLL 100 further includes a low pass filter 120 that smoothes the voltage on the input node IN, and a voltage-controlled oscillator (VCO) 122 that outputs an oscillating signal OSC with a frequency and phase that are defined by the voltage on the input node IN. In addition, a frequency divider 124 divides down the oscillating signal OSC to output the feedback signal FBK with a frequency that is a fractional multiple of the frequency of the oscillating signal OSC. For example, if the oscillating signal OSC has a frequency of 200 MHz and frequency divider 124 divides the signal by two, the feedback signal FBK has a frequency of 100 MHz.
In operation, the phase of the feedback signal FBK, which represents the phase of the oscillating signal OSC, is compared to the phase of the reference signal REF by PFD 110. If the signals are in phase, the up and down signals UP and DN are defined to leave the voltage on the input node IN unchanged.
For example, when the feedback and reference signals FBK and REF are in phase, the up and down signals UP and DN can be equivalent. In this case, switches 114 and 118 are both closed at the same time for the same period of time. Since the charging and discharging currents IC and ID are equivalent, current source 116 sinks all of the current output by current source 112, thereby leaving the voltage on the input node IN unchanged.
If the feedback and reference signals FBK and REF are out of phase, the up and down signals UP and DN are defined to change the voltage on the input node IN to reduce the phase difference between the signals. For example, the up and down signals UP and DN can be output with unequal pulse widths when the feedback and reference signals FBK and REF are out of phase.
Assume that the phase of the oscillating signal OCS output by VCO 122, and thereby the phase of the feedback signal FBK, can be advanced by increasing the voltage on the input node IN. In this case, when the reference clock signal REF leads the feedback signal FBK, the up signal UP can be output with a pulse width that is larger than the pulse width of the down signal DN.
This, in turn, causes switch 114 to be closed for a greater period of time than switch 118. As a result, current source 112 sources more current into the input node IN via charging current IC than is removed by current source 114 via discharging current ID, thereby increasing the voltage on the input node IN.
Similarly, assume that the phase of the oscillating signal OCS output by VCO 122, and thereby the phase of the feedback signal FBK, can be retarded by reducing the voltage on the input node IN. In this case, when the reference clock signal REF lags the feedback signal FBK, the down signal DN can be output with a pulse width that is larger than the pulse width of the up signal UP.
This, in turn, causes switch 118 to be closed for a greater period of time than switch 114. As a result, current source 116 sinks more current from the input node IN via discharging current ID than is added by current source 112 via charging current IC, thereby decreasing the voltage on the input node IN.
It is often advantageous to know the state of the PLL, i.e., whether the oscillating signal output by the PLL is locked onto the reference signal. One prior art technique relies on analog processing of the up and down signals to determine the state of the PLL. Although this technique provides the necessary information, there is a need for other techniques for determining the state of a PLL.
The present invention provides a lock detector that digitally monitors and indicates the state of a phase-locked-loop (PLL), i.e., when an oscillating signal output by the PLL is locked to a reference signal input to the PLL. The PLL has a phase frequency detector (PFD) that outputs an up signal and a down signal that have pulse widths. The pulse widths of the up and down signals are equal when the oscillating signal is locked to the reference signal.
A lock detector in accordance with the present invention includes a dropped lock detection circuit that indicates when the up and down signals output by the PFD are not equivalent. In addition, the lock detector includes a first pulse latch that latches indications that the up and down signals are not equivalent during a first portion of each of a number of time periods.
Further, the lock detector includes a second pulse latch that latches indications that the up and down signals are not equivalent during a second portion of each of the number of time periods. The lock detector also includes an output stage that outputs a lock status signal that indicates whether indications that the up and down signals are not equivalent have been captured by the first pulse latch or the second pulse latch.
The present invention also includes a method for operating a lock detector that digitally monitors and indicates when an oscillating signal output by a PLL is locked to a reference signal input to the PLL. The method includes the step of indicating with a dropped lock detection circuit when the up and down signals output by the PFD are not equivalent.
The method also includes the step of latching with a first pulse latch indications that the up and down signals are not equivalent during a first portion of each of a number of time periods. The method further includes the step of latching with a second pulse latch indications that the up and down signals are not equivalent during a second portion of each of the number of time periods. The method additionally includes the step of outputting with an output stage a lock status signal that indicates whether indications that the up and down signals are not equivalent have been captured by the first pulse latch or the second pulse latch.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.